View CS4327_326845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS4327
Low Cost, 20-Bit, Stereo, Audio D/A Converter
Features Description
The CS4327 is a complete stereo digital-to-analog output system. In addition to the traditional D/A function, the CS4327 includes a digital interpolation filter followed by an 128X oversampled delta-sigma modulator. The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 1 and 50 kHz while maintaining linear phase response simply by changing the master clock frequency. The CS4327 also includes an extremely flexible serial port utilizing mode select pins to support multiple interface formats. The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments. ORDERING INFO CS4327-KS -10 to 70 C 16-pin Plastic SSOP CDB4327 CS4327 Evaluation Board
l 20-Bit Conversion l 108 dB Signal-to-Noise-Ratio (EIAJ) l 100 dB Dynamic Range l Single-Ended Outputs l Complete Stereo DAC System
- 128X Interpolation Filter - Delta-Sigma DAC - Analog Post Filter
l Low Clock Jitter Sensitivity l Filtered Line-Level Outputs l Digital De-emphasis for 32 kHz, 44.1 kHz &
48 kHz
- Linear Phase Filtering - Zero Phase Error Between Channels
I
DIF0
15
DIF1
11
DEM0 DEM1
1 2
VA+
3
VD+
6 16 CMFILT
LRCK 7 SCLK 9 10 SDATA
Serial Input Interface
De-emphasis
Voltage Reference
Interpolator
Delta-Sigma Modulator
DAC
Analog Low-Pass Filter
14
AOUTL
AUTO_MUTE 12
Interpolator
Delta-Sigma Modulator
8 MCLK
DAC
4
Analog Low-Pass Filter
13
AOUTR
5 DGND
AGND
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1997 (All Rights Reserved)
DEC `97 DS190F1 1
CS4327
ANALOG CHARACTERISTICS (TA = 25 C; Internal SCLK; Full-Scale Output Sine wave, 997 Hz;
12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; RL = 10 k; VD+ = VA+ = 5 V; Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted, unless otherwise specified.) Parameter Specified Temperature Operating Range Symbol TA (Note 1) 20-Bit (A-Weighted) 18-Bit (A-Weighted) 16-Bit (A-Weighted) Total Harmonic Distortion + Noise 20-Bit (Note 1) 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (Note 2) THD+N -87 -33 0 0.5465 72 -93 -77 -37 -93 -77 -37 -93 -77 -37 108 -105 0.1 0.5 25/Fs 0.4535 0.002 0.2 dB dB dB dB dB dB dB dB dB dBFS dB dB deg Fs dB Fs dB s dB 93 96 97 100 97 100 93 95 dB dB dB dB dB dB Min -10 Typ Max 70 Unit C
Dynamic Performance Dynamic Range
18-Bit
16-Bit
Idle Channel Noise / Signal-to-Noise-Ratio Interchannel Isolation (1 kHz)
Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz Fs = 48 kHz Deviation from linear phase Passband: to -0.1 dB corner Passband Ripple StopBand StopBand Attenuation Group Delay (Note 3) De-emphasis Error
Notes: 1. Triangular PDF Dithered Data 2. Auto-mute enabled. See parameter definitions. 3. Group Delay for Fs = 48 kHz 25/48 kHz = 520 s
2
DS190F1
CS4327
ANALOG CHARACTERISTICS
Parameter (Continued) Symbol Min 0.95 6 Typ 0.1 2 200 1.0 2.3 Max 5 1.05 100 Unit dB % ppm/C Vrms k pF V
dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Output Full Scale Output Voltage Load Resistance Load Capacitance Output Common Mode Voltage
POWER AND THERMAL CHARACTERISTICS (TA = 25 C; Internal SCLK; Full-Scale Output Sine wave, 997 Hz; 12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; RL = 10 k; VD+ = VD+ = 5 V; Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted, unless otherwise specified.)
Parameter Power Supply Current Normal Operation Symbol IA+ ID+ (IA+) + (ID+) Power Down (IA+) + (ID+) Min PSRR JA Typ 25 12 37 300 185 1.5 60 120 Max 43 215 135 Unit mA mA mA A mW mW dB C C/W
Power Dissipation Power Supply Rejection Ratio (1 kHz) Allowable Junction Temperature Junction to Ambient Thermal Impedance
Normal Operation Power-down
DS190F1
3
CS4327
SWITCHING CHARACTERISTICS
CL = 20 pF) Parameter Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK/LRCK = 384 MCLK/LRCK = 384 MCLK/LRCK = 256 MCLK/LRCK = 256 tsclkl tsclkh tsclkw tslrd tslrs tsdlrs tsdh SCLK/LRCK = 64 tsclkw tsclkr tsdlrs tsdh tsdh Symbol Fs Min 1 10 10 21 21 31 31 20 20
1 ------------------128(Fs)
(TA = 25 C; VA+ = 5.0 V; Inputs: Logic 0 = 0 V, Logic 1 = VD+, Typ t sc lk w ----------------2
Max 50 -
Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External SCLK Mode SCLK Pulse Width Low
SCLK Pulse Width High SCLK Period SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time
20 20 20 20
1 ---------------64(Fs)
Internal SCLK Mode SCLK Period
SCLK rising to LRCK edge SDATA valid to SCLK rising setup time
1 ------------------- + 10 512(Fs) 1 ------------------- + 15 512(Fs) 1 ------------------- + 15 384(Fs)
-
SCLK rising to SDATA hold time MCLK/LRCK = 256 or 512 SCLK rising to SDATA hold time MCLK/LRCK = 384
4
DS190F1
CS4327
LRCK t
slrs
t sclkl t sclkh
t
slrd
SCLK
t
t sdlrs
sdh
SDATA
External Serial Mode Input Timing
LRCK
t
sclkr
SDATA t t
sclkw
sdlrs
t
sdh
*INTERNAL SCLK
Internal Serial Mode Input Timing. * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4327
DS190F1
5
CS4327
DIGITAL CHARACTERISTICS (TA = 25 C; VD+ = 5 V 5%)
Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Digital Input Capacitance Symbol VIH VIL Min 2.0 Typ 10 Max 0.8 10.0 Unit V V A pF
ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.)
Parameter DC Power Supply: Positive Analog Positive Digital |VA+ - VD+| Symbol VA+ VD+ Iin VIND TA Tstg Min -0.3 -0.3 0.0 -0.3 -55 -65 Max 6.0 6.0 0.4 10 (VD+) + 0.4 125 150 Unit V V V mA V C C
Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND = DGND = 0 V; all voltages with respect to ground.) Parameter DC Power Supply: Positive Analog Positive Digital |VA+ - VD+| Symbol VA+ VD+ Min 4.75 4.75 Typ 5.0 5.0 Max 5.25 5.25 0.1 Unit V V V
6
DS190F1
CS4327
2 + 1 F 0.1 F 6 VD+ Mode Select 15 11 DIF0 DIF1 CS4327 7 9 Audio Data Processor 10 1 2 12 AOUTL 14 ANALOG FILTER 3 VA+ + 1 F 0.1 F
+5 V Analog
LRCK SCLK* CMFILT SDATA DEM0 DEM1 AUTO_MUTE 13 ANALOG FILTER 16 + 1 F
8 External Clock
AOUTR MCLK DGND 5 AGND 4
* SCLK must be connected to DGND for operation in Internal SCLK Mode
Figure 1. Typical Connection Diagram
DS190F1
7
CS4327
GENERAL DESCRIPTION
The CS4327 is a complete stereo digital-to-analog system including digital interpolation, 128x fourthorder delta-sigma digital-to-analog conversion, and analog filtering, see Figure 2. This architecture provides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate between 1 and 50 kHz, including the standard audio rates of 48, 44.1 and 32 kHz. The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of laser trimmed resistive DAC architectures by using an inherently linear 1-bit DAC. The advantages of a 1bit DAC include: ideal differential linearity, no distortion mechanisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values.
Delta-Sigma Modulator
The interpolation filter is followed by a fourth-order delta-sigma modulator which converts the 24bit interpolation filter output into 1-bit data at 128x Fs.
Switched-Capacitor Filter
The delta-sigma modulator is followed by a digitalto-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit signal. This technique greatly reduces the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digitalto-analog converters where the magnitude of charge in the D-to-A process is determined by switching a current reference for a period of time defined by the master clock.
Digital Interpolation Filter
The digital interpolation filter increases the sample rate by a factor of 4 and is followed by a 32x digital sample-and-hold to effectively achieve a 128x interpolation filter. This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, Fs. This allows for the selection of a less complex analog filter based on outof-band noise attenuation requirements rather than anti-image filtering. Following the interpolation filter, the resulting frequency spectrum has images of the input signal at multiples of 128x the input sample rate. These images are removed by the external analog filter.
SYSTEM DESIGN Master Clock
The Master Clock, MCLK, is used to operate the digital interpolation filter and the delta-sigma modulator. MCLK must be either 256x, 384x or 512x the desired Input Sample Rate, Fs. Fs is the frequency at which digital audio samples for each channel are input to the DAC and is equal to the LRCK frequency. The MCLK to LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK
Interpolator
Delta-Sigma Modulator
DAC
Analog Low-Pass Filter
AOUT
Figure 2. Block Diagram
8
DS190F1
CS4327
transitions during a single LRCK period. Internal dividers are then set to generate the proper clocks for the digital filter, delta-sigma modulator and switched-capacitor filter. Once the MCLK to LRCK frequency ratio has been detected, the phase and frequency relationship between the two clocks must remain fixed. If during any LRCK this relationship is changed, the CS4327 will reset. Table 1 illustrates the standard audio sample rates and the required MCLK frequencies.
Fs (kHz) 32 44.1 48 MCLK (MHz) 384x 12.2880 16.9344 18.4320
Format 2 is 20-bit left justified, MSB aligned with the leading edge of LRCK. Data is latched on the falling edge of SCLK. The format will support 16 and 18-bit inputs if the data is followed by four or two zeros to simulate a 20-bit input as shown in Figure 4. A very small offset will result if the 18 or 16-bit data is followed by static non-zero data. Format 3 is compatible with the I2S serial data protocol as shown in Figure 5. Notice that the MSB is delayed 1 period of SCLK following the leading edge of LRCK and LRCK is inverted compared to the previous formats. Data is latched on the rising edge of SCLK. Format 3 is a 20-bit I2S format. 18bit or 16-bit I2S can be implemented if the data is followed by two or four zeros to simulate a 20-bit input as shown in Figure 5. A very small offset will result if the 18 or 16-bit data is followed by static non-zero data.
256x 8.1920 11.2896 12.2880
512x 16.3840 22.5792 24.5760
Table 1. Common Clock Frequencies
Serial Data Interface
The serial data interface is accomplished via the serial data input, SDATA, serial data clock, SCLK, and the left/right clock, LRCK. The CS4327 supports four serial data formats which are selected via the digital input format pins DIF0 and DIF1. The different formats control the relationship of LRCK to the serial data and the edge of SCLK used to latch the data into the input buffer. Table 2 lists the formats, along with the associated figure number. The serial data is represented in 2's-complement format with the MSB-first in all four formats.
DIF1 0 0 1 1 DIF0 0 1 0 1 Format 0 1 2 3 Figure 3 3 4 5
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4327 supports both external and internal serial clock generation modes.
External Serial Clock
The CS4327 will enter the external serial clock mode if 15 or more high\low transitions are detected on the SCLK pin during any phase of the LRCK period. When this mode is enabled, internal serial clock mode cannot be accessed without returning to the power down mode.
Internal Serial Clock
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK. The internal SCLK / LRCK ratio is always 64 and operation in this mode is identical to operation with an external serial clock synchronized with LRCK. The SCLK pin must be connected to DGND for proper operation. The internal serial clock mode is advantageous in that there are situations where improper serial
9
Table 2. Digital Input Formats
Formats 0 and 1 are shown in Figure 3. The audio data is right-justified, LSB aligned with the trailing edge of LRCK, and latched into the serial input data buffer on the rising edge of SCLK. Formats 0 and 1 are 16 and 20-bit versions and differ only in the number of data bits required.
DS190F1
CS4327
LRCK
Left Channel
Right Channel
SCLK SDATA 10 Format 0 SDATA Format 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0
Figure 3. Digital Input Format 0 and 1.
LRCK
Left Channel
Right Channel
SCLK
SDATA 16-Bit SDATA 18-Bit SDATA 20-Bit
15 14 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 2 2 1 0 6
2 6
15
17 16
13 12 11 10 9 8 7 6 5 4 3 2 1 0
8 17 16 15 14 13 12 11 10 9 4 4 3 2 1 0
4 8
17
19 18
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6 19 18 17 16 15 14 13 12 11 10 6 5 4 3 2 1 0
10 6
19
Figure 4. Digital Input Format 2.
LRCK
Left Channel
Right Channel
SCLK
SDATA 16-Bit SDATA 18-Bit SDATA 20-Bit
15 12 11 10 9 8 7 6 5 4 3 2 1 0
6 15 14 13 12 11 10 9 8 2 2 1 0
2 6
17
13 12 11 10 9 8 7 6 5 4 3 2 1 0
8 17 16 15 14 13 12 11 10 4 4 3 2 1 0
4 8
19
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6 19 18 17 16 15 14 13 12 10 6 5 4 3 2 1 0
10 6
Figure 5. Digital Input Format 3.
10
DS190F1
CS4327
clock routing on the printed circuit board can degrade system performance. The use of the internal serial clock mode simplifies the routing of the printed circuit board by allowing the serial clock trace to be deleted and avoids possible interference effects.
DEM1 0 0 1 1 DEM0 0 1 0 1 De-emphasis 32 kHz 44.1 kHz 48 kHz OFF
Table 3. De-Emphasis Filter Selection
Auto Mute
An auto-mute function is useful for applications, such as compact disk players, where the idle channel noise must be minimized. The CS4327 will automatically initiate a mute for an idle channel input, where idle channel is defined as an input of static 1's or static 0's during 8192 consecutive LRCK cycles. The mute will be immediately released when non-idle channel data is applied to either the Left or Right channels. This feature is selectable and active only if the AUTO_MUTE pin is low.
Initialization, Calibration and Power-Down
Upon initial power-up, the DAC enters the powerdown mode. The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, one-bit D/A converters and switched-capacitor low-pass filters are powered down. The device will remain in the power-down mode until MCLK and LRCK are presented. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK / LRCK frequency ratio. Power is applied to the internal voltage reference, the D/A converters, switched-capacitor filters and the DAC will begin a common mode bias voltage calibration. This initialization and calibration sequence requires approximately 2700 cycles of LRCK. The CS4327 will enter the power-down mode, within 1 period of LRCK, if either MCLK or LRCK is removed. The initialization sequence, as described above, occurs when MCLK and LRCK are restored. An offset calibration can be invoked by changing the state of Digital Input Format pins, DIF0 and/or DIF1, for at least 3 LRCK cycle. During calibration, a common-mode voltage of approximately 1.8 V appears at the outputs, with approximately a 16 kohm output impedance. Following calibration, the analog output impedance becomes less than 10 ohms and the common mode voltage will move to approximately 2.3 V.
T2 = 15 s
De-Emphasis
Implementation of digital de-emphasis requires reconfiguration of the digital filter to maintain the filter response shown in Figure 6 at multiple sample rates. The CS4327 is capable of digital de-emphasis for 32, 44.1 or 48 kHz sample rates. Table 3 shows the de-emphasis control inputs for DEM 0 and DEM 1.
Gain dB
T1=50 s
0 dB
-10 dB
F1 3.183 kHz
Frequency F2 10.61 kHz
Figure 6. De-emphasis Filter Response
DS190F1
11
CS4327
Combined Digital and Analog Filter Response
The frequency response of the combined analog switched-capacitor and digital filters is shown in Figures 7, 8, and 9. The overall response is clock dependent and will scale with Fs. Note that the response plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs, such as 48 kHz.
Figure 7. CS4327 Combined Digital and Analog Filter Stopband Rejection
Figure 8. CS4327 Combined digital and Analog Filter Passband Response
Figure 9. CS4327 Combined Digital and Analog Filter Transition Band
12
DS190F1
CS4327
Analog Output and Filtering
The CS4327 contains an on-chip buffer amplifier producing single-ended outputs. Each output will produce a nominal 2.83 Vpp (1 Vrms) output with a 2.3 volt common mode for a full scale digital input. The CS4327 filter is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. The second-order lowpass filter with a -3 dB frequency of 50 kHz shown in Figure 10 will give good results in most applications. The design of this filter is discussed in AN55, the Crystal Applications Note "Design Notes for a 2-pole Filter." Figure 11 displays the the output spectrum of the CS4327. Figure 12 displays the output spectrum following the 2-pole filter. Notice the attenuation beyond 50 kHz.
20k
150 pF
10k
3.4k
_ +
100 pF
Figure 10. 2-pole Butterworth Fillter
Figure 11. CS4327 Output Spectrum Fs = 48 kHz
Figure 12. 2-pole Filtered Output Spectrum Fs = 48 kHz
DS190F1
13
CS4327
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4327 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangements with VA+ connected to a clean +5 volt supply. VD+ should be derived from VA+ through a 2 ohm resistor. VD+ should not be used to power additional digital circuitry. All mode pins which require VD+ should be connected to pin 6 of the CS4327. All mode pins which require DGND should be connected to pin 5 of the CS4327. Pins 4 and 5, AGND and DGND, should be connected together at the CS4327. DGND for the CS4327 should not be confused with the ground for the digital section of the system. The CS4327 should be positioned over the analog ground plane near the digital / analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS4327 evaluation board, CDB4327, demonstrates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling capacitors should be located as near to the CS4327 as possible. linearity, one of the key benefits of delta-sigma digital to analog conversion. Figure 15 shows a 16k FFT of a 1 kHz full-scale input signal. The signal has been filtered by a notch filter within the System One to remove the fundamental component of the signal. This minimizes the distortion created in the analyzer analog-to-digital converter. This technique is discussed by Audio Precision in the 10th anniversary addition of AUDIO.TST. Figure 16 shows a 16k FFT of a 1 kHz -20 dBFS input signal. The signal has been filtered by a notch filter within the System One to remove the fundamental component of the signal. Figure 17 shows a 16k FFT of a 1 kHz -60 dBFS input signal. Figure 18 shows the fade-to-noise linearity. The input signal is a dithered 20-bit 500 Hz sine wave which fades from -60 to -120 dBFS. During the fade, the output from the CS4327 is measured and compared to the ideal level. Notice the very close tracking of the output level to the ideal, even at low level inputs. The gradual shift of the plot away from zero at signals levels < -110 dB is caused by the background noise starting to dominate the measurement.
Performance Plots
The following collection of CS4327 measurement plots were taken from the CDB4327 evaluation board using the Audio Precision Dual Domain System One. Figure 13 shows the frequency response at a 48 kHz sample rate. The response is flat to 20 kHz 0.1 dB as specified. Figure 14 shows THD+N versus signal amplitude for a 1 kHz 20-bit dithered input signal. Notice that the there is no increase in distortion as the signal level decreases. This indicates very good low-level
14
DS190F1
CS4327
Figure 13. Frequency Response
Figure 14. THD+N vs. Amplitude
Figure 15. 0 dBFS FFT
Figure 16. -20 dBFS FFT
Figure 17. -60 dBFS FFT
Figure 18. Fade-to-Noise Linearity
DS190F1
15
CS4327
PIN DESCRIPTIONS
DEM0
DEM1 VA+ AGND DGND VD+ LRCK MCLK
1 2 3
4
16 15 14
13
CMFILT
DIF0 AOUTL AOUTR AUTO_MUTE DIF1 SDATA SCLK
5 6
7
12 11
10
8
9
Power Supply Connections
VA+ - Positive Analog Power, PIN 3. Positive analog supply. Nominally +5 volts. VD+ - Positive Digital Power, PIN 6. Positive supply for the digital section. Nominally +5 volts. AGND - Analog Ground, PIN 4. Analog ground reference. DGND - Digital Ground, PIN 5. Ground for the digital section. Analog Outputs AOUTR - Right Channel Analog Output, PIN 13. Analog output connection for the Right channel output. Nominally 1 Vrms for full-scale digital input signal. AOUTL - Left Channel Analog Output, PIN 14. Analog output connection for the Left channel outputs. Nominally 1 Vrms for full-scale digital input signal.
16
DS190F1
CS4327
Digital Inputs
MCLK - Clock Input, PIN 8. The frequency must be either 256x, 384x or 512x the input sample rate (Fs). LRCK - Left/Right Clock, PIN 7. This input determines which channel is currently being input on the Serial Data Input pin, SDATA. The format of LRCK is controlled by DIF0 and DIF1. SCLK - Serial Bit Input Clock, PIN 9. Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch SDATA is controlled by DIF0 and DIF1. SDATA - Serial Data Input, PIN 10. Two's complement MSB-first serial data of either 16, 18 or 20 bits is input on this pin. The data is clocked into the CS4327 via the SCLK clock, and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0 and DIF1. DIF0, DIF1 - Digital Input Format, PINS 15, 11 These two pins select one of four formats for the incoming serial data stream. These pins set the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in Table 2. DEM0, DEM1 - De-Emphasis Select, PINS 1, 2. Controls the activation of the standard 50/15 s de-emphasis filter for either 32, 44.1 or 48 kHz sample rates. AUTO_MUTE - Automatic Mute on Idle Channel Input, PIN 12. When AUTO_MUTE is low the analog outputs are muted following an idle channel detection. Idle channel is defined as an input of static 1's or static 0's during 8192 consecutive LRCK cycles. Mute is canceled with the return of active channel input data. CMFILT - Common Mode Filter, PIN 16 Used to filter the common mode output voltage with a 1 F capacitor. This pin is not intended to supply any current and should not be used for the generation of an external bias voltage.
DS190F1
17
CS4327
PARAMETER DEFINITIONS
Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. De-Emphasis Error A measure of the difference between the ideal de-emphasis filter and the actual de-emphasis filter response. Measured from 10 Hz to 20 kHz. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
18 DS190F1
CS4327
PACKAGE DIMENSIONS
N
E
SSOP Package Dimensions
123
TOP VIEW D1 A2 A
e
E1
1
A1
b SIDE VIEW
2
Seating Plane
L
END VIEW
NOTES: 1. DIMENSIONS D AND E1 ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.20mm PER SIDE. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. 3. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS.
DIM A A1 A2 b D E E1 e L N
MILLIMETERS MIN NOM MAX 2.13 0.05 0.15 0.25 1.62 1.75 1.88 0.22 0.30 0.38 see other table 7.40 7.80 8.20 5.00 5.30 5.60 0.61 0.65 0.69 0.63 0.90 1.03 see other table 0 4 8
INCHES MIN NOM MAX Note - 0.084 0.002 0.006 0.010 0.064 0.070 0.074 0.009 0.012 0.015 2, 3 see other table 1 0.291 0.307 0.323 0.197 0.209 0.220 1 0.024 0.026 0.027 0.025 0.035 0.040 see other table 0 4 8
D
N 16 20 28
MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX Note 5.90 6.20 6.50 0.232 0.244 0.256 1 6.90 7.20 7.50 0.272 0.283 0.295 1 9.90 10.20 10.50 0.390 0.402 0.413 1
DS190F1
19
* Notes *
CDB4327
Evaluation Board for CS4327
Features General Description
The CDB4327 evaluation board is an excellent means for quickly evaluating the CS4327 20-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source and a power supply. Analog outputs are provided via RCA connectors for both channels. The CS8412 digital audio receiver I.C. provides the system timing necessary to operate the CS4327 and will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development.
*
Demonstrates recommended layout and grounding arrangements
* CS8412 Receives AES/EBU, S/PDIF,
& EIAJ-340 Compatible Digital Audio
* Digital and Analog Patch Areas * Requires only a digital signal source
and power supplies for a complete Digital-to-Analog-Converter system
ORDERING INFORMATION:
CDB4327
I/O for Clocks and Data
CS8412 Digital Audio Interface
CS4327
Analog Filter
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1997 (All Rights Reserved)
DEC '95 DS190DB1 21
CDB4327
CDB4327 System Overview The CDB4327 evaluation board is an excellent means of quickly evaluating the CS4327. The CS8412 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4327 schematic has been partitioned into 7 schematics shown in Figures 2 through 8. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. CS4327 Digital to Analog Converter A description of the CS4327 is included in the CS4327 data sheet. CS8412 Digital Audio Receiver Data Format The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 8. The outputs of the CS8412 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256Fs master clock. The operation of the CS8412 and a discussion of the digital audio interface are included in the 1994 Crystal Semiconductor Audio Data Book. During normal operation, the CS8412 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8412 to decode and supply the de-emphasis bit from the digital audio interface for control of the CS4327 de-emphasis filter via pin 3, CC/F0, of the CS8412. When the Error Information Switch is activated, the CS8412 operates in the Error and Frequency
22 DS190DB1
information mode. The information displayed by the LED's can be decoded by consulting the CS8412 data sheet. If the Error Information Switch is activated, the CC/F0 output has no relation to the de-emphasis bit and it is likely that the de-emphasis control for the CS4327 will be erroneous and produce an incorrect audio output. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8412. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, Figure 7. It is not necessary to select the active input. However, both inputs can not be driven simultaneously.
The CS4327 must be configured to be compatible with the incoming data and can be set with DIF0 and DIF1. The CS8412 data format can be set with the M0, M1, M2 and M3. There are several data formats which the CS8412 can produce that are compatible with CS4327. Refer to Table 2 for one possibility. Power Supply Circuitry Power is supplied to the evaluation board by four binding posts, Figure 9. The +5 Volt input supplies power to the CS4327 (through VA+), the CS8412 (through VA+ and VD+), and the +5 Volt digital circuitry (through VD+). The +/- 12 Volt input supplies power to the analog filter circuitry.
CDB4327
Input/Output for Clocks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 6. The 74HC243 transceiver functions as an I/O buffer where the CLK SOURCE jumper determines if the transceiver operates as a transmitter or receiver. The transceiver operates as a transmitter with the CLK SOURCE jumper in the 8412 position. LRCK, SDATA, and SCLK from the CS8412 will be available on J1. J22 must be in the 0 position and J23 must be in the 1 position for MCLK to be an output and to avoid bus contention on MCLK. The transceiver operates as a receiver with the CLK SOURCE jumper in the EXTERNAL position. LRCK, SDATA and SCLK on J1 become inputs. The CS8412 must be removed from the evaluation board for operation in this mode. There are 2 options for the source of MCLK in the EXT CLK source mode. MCLK can be an input with J23 in the 1 position and J22 in the 0 position. However, the recommended mode of operation is to generate MCLK on the evaluation board. MCLK becomes an output with LRCK, SCLK and SDATA inputs. This technique insures that the CS4327 receives a jitter free clock to maximize performance. This can be accomplished by installing a crystal oscillator into U4, see Figure 8 (the socket for U4 is located within the footprint for the CS8412) and placing J22 in the 1 position and J23 in the 0 position. Analog Filter The design of the second-order Butterworth lowpass filter, Figure 5, is discussed in the CS4327 data sheet and the applications note "Design Notes for a 2-pole Filter." Grounding and Power Supply Decoupling The CS4327 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 Volt supply. VD1+ is derived from VA+ through a 2 ohm resistor. VD1+ should not used for any additional digital circuitry. Ideally, all mode pins which require VD1+ should be connected to pin 6 of the CS4327 and all mode pins which require DGND should connected to pin 5 of the CS4327. AGND and DGND, Pins 4 and 5, are connected together at the CS4327. The evaluation board has separate analog and digital regions with individual ground planes. DGND for the CS4327 should not be confused with the ground for the digital section of the system (GND). The CS4327 is positioned over the analog ground plane near the digital/analog ground plane split. These ground planes are connected elsewhere on the board. This layout technique is used to minimizing digital noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the CS4327 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large reductions in radiated noise effects.
DS190DB1
23
CDB4327
CONNECTOR +5V +/- 12V GND Digital input Optical input J1 AOUTL AOUTR
INPUT/OUTPUT input input input input input input/output output output
SIGNAL PRESENT +5 Volts for the CS4327, CS8412, and digital section +/- 12 Volts for analog filter section ground connection from power supply digital audio interface input via coax digital audio interface input via optical I/O for system clocks and digital audio data left channel analog output right channel analog output
Table 1. System Connections
JUMPER CSLR/FCK Clock Select J22 J23 M0 M1 M2 M3 auto_mute DEM0 DEM1 DIF0 DIF1 SCLK DEM_8412
PURPOSE Selects channel for CS8412 channel status information Selects source of system clocks and data Selects MCLK as input or output CS8412 mode select
POSITION L R *8412 EXT 0 1 *Low *Low *Low *Low *Low High *High *Low *Low *High *INT EXT *Low High
FUNCTION SELECTED See CS8412 data sheet for details CS8412 clock/data source External clock/data source See Input/Output for Clocks and Data section of text See CS8412 data sheet for details
CS4327 Auto Mute De-emphasis select CS4327 digital input format CS4327 SCLK Mode Selects source of deemphasis control
On Off See CS4327 data sheet for details set for 44.1 kHz See CS4327 data sheet for details Internal SCLK Mode External SCLK Mode CS8412 de-emphasis De-emphasis input static high
* Default setting from factory
Table 2. CDB4327 Jumper Selectable Options 24 DS190DB1
CDB4327
Digital Audio Input fig 7
RXN RXP
I/O for Clocks and Data
fig 6
MCLK
LRCK SCLK SDATA
AOUTL
CS8412 Digital Audio Interface
CS4327
AOUTR
Analog Filter
fig 5
fig 8
AUTOMUTE
fig 2
DEM0
DEM1
DIF0
De-emphasis Mode Selection
fig 3
Auto Mute Select and Format Select fig 5
Figure 1. System Block Diagram and Signal Flow
DS190DB1
DIF1
25
26
CDB4327
DB190DB1
Figure 2. CS4327 and Connections
CDB4327
Figure 3. De-Emphasis Mode Selection
Figure 4. Auto-Mute Select and Format Select
DB190DB1
27
CDB4327
NOTE: Right Channel components in parentheses
Figure 5. 2-Pole Analog Filter
Figure 6. I/O Interface for Clocks and Data
28
DB190DB1
CDB4327
OPT1 Toshiba TORX173 optical receiver available from Insight Electronics
Figure 7. Digital Audio Input
DB190DB1
29
30 Note: U2 and U4 can not be installed simultaneously DB190DB1
CDB4327
Figure 8. CS8412 and Connections
CDB4327
Figure 9. Power Supply Connections
DB190DB1
31
CDB4327
Figure 10. CDB4327 Component Side Silkscreen
32
DB190DB1
CDB4327
Figure 11. CDB4327 Component Side (top)
DB190DB1
33
CDB4327
Figure 12. CDB4327 Solder Side (bottom)
34
DB190DB1
* Notes *

▲Up To Search▲

Price & Availability of CS4327

	To Download CS4327 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .